In order to form a hole as a contact hole on an insulation film or the like, a plasma processing apparatus performs a dry etching such as a high anisotropic reactive ion etching or the like. FIG. 6 shows a case of etching an object to be processed, e.g., a wafer in which an insulation film 202, a hard mask 203 formed of SiO2 or the like, an anti-reflection coating 204 and a resist film 205 are laminated on an underlayer 201 in order.
First of all, as depicted in FIG. 6A, an opening 205A is formed in the resist film 205 by employing a photolithography process. Next, as illustrated in FIG. 6B, a dry etching is performed on the anti-reflection coating 204, the hard mask 203 and the insulation film 202 by using the resist film 205 as a mask until the underlayer 201 is exposed, thereby forming an opening 206. During the dry etching, the underlayer 201 as well as a sidewall of the opening 206 is irradiated by reactive ions or the like. Accordingly, the underlayer 201 is damaged as depicted in FIG. 6B and, further, the damage inflicted on the underlayer 201 hinders a wiring process or the like to be performed.
As described in FIG. 6C, a defective layer 206A has been removed through a conventional wet etching process. However, in case of the wet etching process, since it is difficult to find out the exact thickness of the defective layer 206A to be removed, it is very difficult to precisely remove only the defective layer 206A and, thus, a surface of the underlayer 201 tends to be overetched, thereby deteriorating a fabrication accuracy. Therefore, there is suggested a technique for removing the defective layer 206A while maintaining the fabrication accuracy for forming the opening 206 to the utmost in Japanese Patent Application Nos. H05-182871, H07-167680 and H08-144008 (hereinafter, referred to as Patent documents 1 to 3).
For example, the Patent document 1 suggests a semiconductor device fabrication method involving forming an insulation film on an underlayer of a wafer, dry etching the insulation film by applying a patterned resist film as a mask, exposing the underlayer through an opening generated by dry etching, forming a selective oxide layer by oxidizing a defective layer formed on a surface of the underlayer during the dry etching process, and removing the selective oxide layer by a wet etching. In this method, while the defective layer formed on the surface of the underlayer is removed, an overetching onto the underlayer is suppressed by converting the defective layer into the selective oxide layer by oxidizing it first before it is removed.
The Patent document 2 suggests a semiconductor device fabrication method involving a first plasma etching process in which a part of an inter-layer insulation film is etched along a thickness direction thereof until a surface of a device area is about to be exposed and a second plasma etching process in which a remaining part of the inter-layer insulation film in the thickness direction thereof is etched by a gas capable of generating halogen-based chemical species other than fluorine-based chemical species. In this method, the etching is performed by using the gas capable of generating halogen-based chemical species other than fluorine-based chemical species, thereby suppressing carbon or fluorine contamination on the device area or a generation of a defective layer thereon.
The Patent document 3 suggests a semiconductor device fabrication method involving dry etching an insulation film formed on an underlayer of a wafer, and removing a defective layer formed on the surface of the underlayer by irradiating accelerated oxygen ions thereon through an opening of the insulation film. In this method, since fluorine is not used for removing the defective layer, the surface of the underlayer is not etched. As a result, irregularities are not generated on the surface of the underlayer.
In the conventional method of the Patent document 1, the insulation film is dry etched until the silicon underlayer is exposed and the defective layer formed on the silicon underlayer is oxidized and converted into a selective oxide layer and, then, the selective oxide layer is wet etched. Accordingly, in case an underlayer or a device area is formed on the surface of the silicon substrate, an etching selectivity of the insulation film against the underlayer or the device region can be low during the dry etching process, and, further, the defective layer formed on the surface of the underlayer or the device area is removed by the wet etching. Therefore, it is possible to precisely and exclusively etch the insulation film only, resulting in the erosion of the underlayer or the device area.
Meanwhile, the underlayer keeps getting thinner along with a trend for high integration and high density of a semiconductor device. For example, a film thickness currently ranging from 50 nm to 100 nm is expected to be reduced to range from 20 nm to 30 nm in a near future. Therefore, with the etching method of the Patent document 1, it is not possible to cope with the trend for the thinner semiconductor underlayer.
Further, in the conventional method of the Patent document 2, the etching is performed by using the gas capable of generating halogen-based chemical species other than fluorine-based chemical species, thereby enabling to suppress carbon or fluorine contamination on the device area or a generation of a defective layer thereon. However, it is not possible to completely prevent the contamination from the halogen-based chemical species (elements such as Cl, Br or the like) and the generation of the defective layer. Consequently, with the etching method of the Patent document 2, it is not possible to cope with the trend for the thinner underlayer.
Furthermore, in the conventional method of the Patent document 3, since the defective layer formed on the surface of the underlayer is removed by irradiating accelerated oxygen ions thereon, energy of the oxygen ions should be precisely controlled such that the surface of the underlayer is not etched by the oxygen ions.